This is the new front page for the F-CPU website. Since 2015, everything is being rebuilt from scratch, please be patient.
Today, the Freedom CPU Project's goal is to create and distribute the source code of a microprocessor core under a copyleft license: all the VHDL sources, resources and most tools are Free as in Free Speech. When it was created in 1999, the F-CPU Core #0 (FC0) was the first purely SIMD superpipelined RISC CPU core that could handle 64-bit data and wider.
After the F-CPU project's freeze in 2004 and some explorations of embedded designs, the tools developed for yasep.org are getting mature enough to consider a reboot of this project, with an updated framework, a better roadmap and new direction.
In 2017, some architectural breakthroughs inspired the creation of FC1, which takes most of the great features of FC0 and gets rid of some compromises and misguided design choices. Not only could the core run faster, but it can effortlessly decode and execute of up to 4 instructions per cyle.